Regviz

NXP Semiconductors /MIMXRT1011 /ADC_ETC /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/MIMXRT1011/ADC_ETC/CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRIG_ENABLE0 (EXT0_TRIG_ENABLE)EXT0_TRIG_ENABLE 0EXT0_TRIG_PRIORITY 0 (EXT1_TRIG_ENABLE)EXT1_TRIG_ENABLE 0EXT1_TRIG_PRIORITY 0PRE_DIVIDER0 (DMA_MODE_SEL)DMA_MODE_SEL 0 (TSC_BYPASS)TSC_BYPASS 0 (SOFTRST)SOFTRST

Description

ADC_ETC Global Control Register

Fields

TRIG_ENABLE

TRIG enable register
EXT0_TRIG_ENABLE

TSC0 TRIG enable register. 1’b1: enable external TSC0 trigger. 1’b0: disable external TSC0 trigger.
EXT0_TRIG_PRIORITY

External TSC0 trigger priority, 7 is Highest, 0 is lowest .
EXT1_TRIG_ENABLE

TSC1 TRIG enable register. 1’b1: enable external TSC1 trigger. 1’b0: disable external TSC1 trigger.
EXT1_TRIG_PRIORITY

External TSC1 trigger priority, 7 is Highest, 0 is lowest .
PRE_DIVIDER

Pre-divider for trig delay and interval .
DMA_MODE_SEL

1’b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared
TSC_BYPASS

1’b1: TSC is bypassed to ADC2. 1’b0: TSC not bypassed. To use ADC2, this bit should be cleared.
SOFTRST

Software reset, high active. When write 1 ,all logical will be reset.

Links

()

Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data